1. Field of the Invention
The present invention relates to a semiconductor device and methods of forming and operating the same, and more particularly, to a non-volatile memory device and methods of forming and operating the same.
2. Description of the Related Art
In a non-volatile memory device, the structure of an Electrically Erasable Programmable Read-Only Memory (EEPROM) cell includes one memory transistor and one select transistor positioned between a common source line and a bit line. The memory transistor includes a floating gate that stores charge, a control gate formed on the top of the floating gate to control the floating gate, and a tunnel insulation layer that operates as a path through which charge migrates by Fowler-Nordheim (F-N) tunneling during writing and erasing operations. The select transistor serves to deliver a voltage applied from a bit line to the memory transistor during writing and erasing operations. The memory transistor and the select transistor make a pair and are symmetrically disposed with respect to a common source line. That is, two adjacent memory transistors are configured to share the common source line therebetween. During the writing and erasing of a selected transistor, a disturbance can occur, where an unselected memory transistor sharing the common source line can inadvertently become written to or erased. As a result, distribution of a threshold voltage becomes faulty.
To prevent such faulty distribution, a structure can be introduced, in which an additional select transistor is disposed between the memory transistor and the common source line to control a voltage applied from the common source line. However, since three transistors are required for this structure, the degree of device integration deteriorates.